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TLC1543 数据表(PDF) 5 Page - Texas Instruments |
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TLC1543 数据表(HTML) 5 Page - Texas Instruments |
5 / 27 page TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS052E – MARCH 1992 – OCTOBER 1998 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer In this mode, CS is inactive (high) between serial I/O CLOCK transfers, and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. mode 4: fast mode, CS active (low) continuously, 16-clock transfer In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous conversion to appear immediately on this output. slow modes In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must occur before the conversion period is complete; otherwise, the device loses synchronization with the host-serial interface and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must occur within 9.5 µs after the tenth I/O clock falling edge. mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. mode 6: slow mode, CS active (low) continuously, 16-clock transfer In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next 16-clock transfer initiated by the serial interface. address bits The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal (MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address selects one of 14 inputs (11 analog inputs or three internal test inputs). analog inputs and test modes The 11 analog inputs and the three internal test inputs are selected by the 14-channel multiplexer according to the input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching. Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs. |
类似零件编号 - TLC1543 |
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类似说明 - TLC1543 |
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