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TL16C552AMPN 数据表(PDF) 7 Page - Texas Instruments |
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TL16C552AMPN 数据表(HTML) 7 Page - Texas Instruments |
7 / 39 page TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD 4.75 5 5.25 V Clock high-level input voltage, VIH(CLK) 2 VDD V Clock low-level input voltage, VIL(CLK) 0 0.8 V High-level input voltage, VIH 2 VDD V Low-level input voltage, VIL 0 0.8 V Clock frequency, fclock 16 MHz Operating free air temperature TA I suffix –40 85 °C Operating free-air temperature, TA M suffix –55 125 °C package thermal characteristics PARAMETER TEST CONDITIONS FN Package HV Package UNIT PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT R θJA Junction-to-ambient thermal impedance Board mounted, no air flow 52 74 °C/W R θJC Junction-to-case thermal impedance 14 3 °C/W TJ Junction temperature 115 150 °C/W electrical characteristics over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High-level output voltage IOH = – 12 mA for PD0 – PD7, IOH = – 4 mA for all other outputs (see Note 2), 2.4 V VOL Low-level output voltage IOL = 12 mA for PD0 – PD7, IOL = 12 mA for INIT, AFD, STB, and SLIN, IOL = 4 mA for all other outputs 0.4 V II Input current VDD = 5.25 V (see Note 3), All other terminals are floating ±10 µA II(CLK) Clock input current VI = 0 to 5.25 V ±10 µA VDD =5 25 V VO = 0 with chip deselected or IOZ High-impedance output current VDD = 5.25 V, VO = 0 with chi deselected or VO 5 25 V with chip and write mode selected (see Note 2) ±20 µA IOZ High im edance out ut current VO = 5.25 V with chip and write mode selected (see Note 2) ±20 µA V 5 25 V No loads on outputs IDD Supply current VDD = 5.25 V, No loads on outputs, 50 mA IDD Supply current DD Inputs at 0 8Vor2V fclock = 8 MHz 50 mA In uts at 0.8 V or 2 V, fclock = 8 MHz NOTES: 2. Excluding INIT, AFD, STB, and SLIN. They are open-drain terminals with an internal pullup resistor to VDD of approximately 10 KΩ. 3. Excluding the TRI input terminal. It contains an internal pulldown resistor of approximately 5 k Ω. clock timing requirements over recommended ranges of operating free-air temperature and supply voltage MIN MAX UNIT tw1 Pulse duration, CLK ↑ (external clock) (see Figure 1) 31 ns tw2 Pulse duration, CLK ↓ (external clock) (see Figure 1) 31 ns tw3 Pulse duration, RESET 1000 ns |
类似零件编号 - TL16C552AMPN |
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类似说明 - TL16C552AMPN |
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