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SN74ALVCH16903DGG 数据表(PDF) 9 Page - Texas Instruments |
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SN74ALVCH16903DGG 数据表(HTML) 9 Page - Texas Instruments |
9 / 12 page SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V From Output Under Test PARI/O LOAD CIRCUIT tPLH tPHL VCC/2 VCC/2 VCC 0 V VCC/2 VCC/2 VOH VOL Input VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. C. tPLH and tPHL are the same as tpd. CL = 0.6 pF (see Note A) Test Point PARI/O of Second ALVCH16903 CL = 0.6 pF (see Note A) ZO = 52 Ω Td = 63 ps Figure 2. Load Circuit and Voltage Waveforms From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT RL = 10 Ω tPLH tPHL VCC/2 VCC/2 VCC 0 V VCC/2 VCC/2 VOH VOL Input VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Test Point NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. Figure 3. Load Circuit and Voltage Waveforms |
类似零件编号 - SN74ALVCH16903DGG |
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类似说明 - SN74ALVCH16903DGG |
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