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SN74ALVCH16832 数据表(PDF) 1 Page - Texas Instruments |
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SN74ALVCH16832 数据表(HTML) 1 Page - Texas Instruments |
1 / 9 page SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES098D – MAY 1997 – REVISED FEBRUARY 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Member of the Texas Instruments Widebus ™ Family D EPIC ™ (Enhanced-Performance Implanted CMOS) Submicron Process D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 250 mA Per JESD 17 D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D Packaged in Thin Shrink Small-Outline Package description This 1-bit to 4-bit address register/driver is designed for 1.65-V to 3.6-V VCC operation. This device is ideal for use in applications in which a single address bus is driving four separate memory locations. The SN74ALVCH16832 can be used as a buffer or a register, depending on the logic level of the select (SEL) input. When SEL is a logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by the two output-enable (OE) inputs. Each OE controls two groups of seven outputs. When SEL is a logic low, the device is in the register mode. The register is an edge-triggered D-type flip-flop. On the positive transition of the clock (CLK) input, data at the A inputs is stored in the internal registers. OE operates the same as in the buffer mode. When OE is a logic low, the outputs are in a normal logic state (high or low logic level). When OE is a logic high, the outputs are in the high-impedance state. Neither SEL nor OE affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16832 is characterized for operation from –40 °C to 85°C. Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. DGG PACKAGE (TOP VIEW) NC – No internal connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 4Y1 3Y1 GND 2Y1 1Y1 VCC A1 GND A2 GND A3 VCC NC GND CLK OE1 OE2 SEL GND A4 A5 VCC GND A6 GND A7 VCC 4Y7 3Y7 GND 2Y7 1Y7 1Y2 2Y2 GND 3Y2 4Y2 VCC 1Y3 2Y3 GND 3Y3 4Y3 GND VCC GND 1Y4 2Y4 3Y4 4Y4 GND 1Y5 2Y5 VCC 3Y5 4Y5 GND GND VCC 1Y6 2Y6 GND 3Y6 4Y6 |
类似零件编号 - SN74ALVCH16832 |
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类似说明 - SN74ALVCH16832 |
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