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AD7846JP 数据表(PDF) 5 Page - Analog Devices |
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AD7846JP 数据表(HTML) 5 Page - Analog Devices |
5 / 16 page AD7846 REV. E –5– PIN FUNCTION DESCRIPTION Pin Mnemonic Description 1–3 DB2–DB0 Data I/O pins. DB0 is LSB. 4VDD Positive supply for analog circuitry. This is +15 V nominal. 5VOUT DAC output voltage pin. 6RIN Input to summing resistor of DAC output amplifier. This is used to select output voltage ranges. See Table I. 7VREF+ VREF+ Input. The DAC is specified for VREF+ = +5 V. 8VREF– VREF– Input. For unipolar operation con- nect VREF– to 0 V and for bipolar operation connect it to –5 V. The device is specified for both conditions. 9VSS Negative supply for the analog circuitry. This is –15 V nominal. 10–19 DB15–DB6 Data I/O pins. DB15 is MSB. 20 DGND Ground pin for digital circuitry. 21 VCC Positive supply for digital circuitry. This is +5 V nominal. 22 R/ W R/ W input. This can be used to load data to the DAC or to read back the DAC latch contents. 23 CS Chip select input. This selects the device. 24 CLR Clear input. The DAC can be cleared to 000 . . . 000 or 100 . . . 000. See Table II. 25 LDAC Asynchronous load input to DAC. 26–28 DB5–DB3 Data I/O pins. Table I. Output Voltage Ranges Output Range VREF+ VREF– RIN 0 V to +5 V +5 V 0 V VOUT 0 V to +10 V +5 V 0 V 0 V +5 V to –5 V +5 V –5 V VOUT +5 V to –5 V +5 V 0 V +5 V +10 V to –10 V +5 V –5 V 0 V PIN CONFIGURATIONS DIP TOP VIEW (Not to Scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AD7846 DB11 DB12 DB13 DB14 DB15 VSS VREF– DB2 DB1 DB0 VDD VREF+ RIN VOUT DB10 DB9 DB8 DB7 DB6 DGND DB3 DB4 DB5 LDAC R/ W CS CLR VCC PLCC 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) 12 13 14 15 16 17 18 LDAC CLR CS R/ W DGND DB6 VOUT RIN VREF+ VREF– VSS DB15 DB14 AD7846 VCC |
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