SN74ACT8994

DIGITAL BUS MONITOR

IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

SCAS196E – JULY 1990 – REVISED DECEMBER 1996

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POST OFFICE BOX 655303

event-qualification register 2 (continued)

During execution of the DMA instructions, EQR2 is configured as a 48-bit register containing only the three

16-bit data segments. Using DMA instructions allows a continuous stream of data to be loaded or unloaded from

the register files. After each 48th bit of the data stream has been shifted to or from the register files, the register

file addresses are automatically incremented and the first data bit of the next address is shifted.

header register

The header register (HR) is an 8-bit register that initiates DMA write operations on the RAM and on the EQR2

register files. When a DMA write instruction is active, the data being shifted from TDI to TDO is compared against

the current value of the HR and the DMA write operation begins after a match is found. When the value of the

HR is set to 00h, DMA write operations can only be initiated by the TAP and are not initiated by the TDI-to-TDO

data flow.

random-access memory register

The random-access memory register (RAMR) is used to access the 1024-word RAM. Depending on the current

instruction, it is either 16 bits or 26 bits in length and can be thought of as a 16-bit data segment and a 10-bit

address segment.

The RAMR can be accessed using IEEE-Standard-1149.1-1990-compatible instructions or DMA instructions.

When using the IEEE-Standard-1149.1-1990-compatible instructions, RAMR is configured as a 26-bit register.

The data appearing in the 16-bit data segment is loaded into or out of the address specified by the register’s

10-bit address.

During execution of the DMA instructions, RAMR is configured as a 16-bit register containing only the 16-bit

data segment. Using DMA instructions allows a continuous stream of data to be loaded or unloaded from the

register. After each 16th bit of the data stream has been shifted to or from the register, the address is

automatically incremented and the first data bit of the next address is shifted.

test-cell register

The test-cell register (TCR) is a 16-bit register. It can perform PSA operations on the data inputs or on the

contents of RAM. The resulting signature can be scanned out and compared against an expected value. The

TCR is also used during test operations to capture the current value of the data bus.

test operations

The primary function of the DBM is to perform test operations while monitoring a digital bus. The test operations

can be initiated by system conditions (on-line mode) or independent of system conditions (off-line mode). The

description of each of the system test operations follows.

sample

The data at the D inputs is captured in the test-cell register and can be shifted out via TDO for inspection.

parallel-signature analysis

A parallel-signature analysis (PSA) is performed on the data appearing at the D inputs. The test-cell register

is configured as a linear-feedback shift register that compresses the data into a signature. The user can

configure the device to mask data bits from PSA operations and control the feedback of the linear-feedback shift

register. When an input is masked, it is ignored and has no effect on the generated signature.

trace

The data at the D inputs is stored in the RAM. The RAM address is automatically incremented after each write

cycle. The device can be configured to clear the RAM address to 000h at the beginning of test execution. It also

can be configured to allow write cycles to continue after the maximum address 3FFh is reached (thus clearing

the address to 000h and overwriting data).