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SN74GTL16612A 数据表(PDF) 4 Page - Texas Instruments |
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SN74GTL16612A 数据表(HTML) 4 Page - Texas Instruments |
4 / 15 page www.ti.com 1D C1 CLK 1D C1 CLK B1 OEAB CEAB CLKAB LEAB LEBA CLKBA CEBA OEBA A1 To 17 Other Channels CE CE 1 56 55 2 28 30 29 27 3 54 VREF 35 SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS SCES187D – JANUARY 1999 – REVISED JULY 2005 FUNCTION TABLE(1) INPUTS OUTPUT MODE B CEAB OEAB LEAB CLKAB A X H X X X Z Isolation L L L H X B0(2) Latched storage of A data L L L L X B0(3) X L H X L L Transparent X L H X H H L L L ↑ L L Clocked storage of A data L L L ↑ H H H L L X X B0(3) Clock inhibit (1) A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA. (2) Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low (3) Output level before the indicated steady-state input conditions were established LOGIC DIAGRAM (POSITIVE LOGIC) 4 |
类似零件编号 - SN74GTL16612A |
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类似说明 - SN74GTL16612A |
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