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DAC-HK12BMM-2 数据表(PDF) 2 Page - Murata Power Solutions Inc.

部件名 DAC-HK12BMM-2
功能描述  High-Performance, 12-Bit DAC?셲 with Input Registers
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制造商  MURATA-PS [Murata Power Solutions Inc.]
网页  http://www.murata-ps.com
标志 MURATA-PS - Murata Power Solutions Inc.

DAC-HK12BMM-2 数据表(HTML) 2 Page - Murata Power Solutions Inc.

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DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1194 (U.S.A.) Tel: 508-339-3000 Fax: 508-339-6356 • For immediate assistance 800-233-2765
DAC-HK Series
®
®
INPUTS
Resolution
12 bits
Coding, Unipolar Output
Straight binary
Coding, Bipolar Output
Offset binary, two’s complement
Input Logic Level, Bit ON ("1")
+2.0V to +5.5V
Input Logic Level, Bit OFF ("0")
0V to +0.8V
Logic Loading
1 LSTTL load
Load Input
High (“1”) = hold data
Low (“0”) = transfer data
Load Input Loading
3 LSTTL loads
PERFORMANCE
Nonlinearity Error, max.
±1/2LSB
Differential Nonlinearity Error, max.
±3/4LSB
Gain Error, Before Trimming
±0.1%
Zero Error, Before Trimming
±0.1% of FSR
Gain Tempco, max.
±20ppm/°C
Zero Tempco, Unipolar, max.
±5ppm/°C of FSR
Offset Tempco, Bipolar, max.
±10ppm/°C of FSR
Diff. Nonlinearity Tempco, max.
±2ppm/°C of FSR
Monotonicity
Guaranteed over temperature
Settling Time, 5V Change
3
µs
Settling Time, 10V Change
3
µs
Settling Time, 20V Change
4
µs
Settling Time, 1LSB Change
800ns
Slew Rate
±20V/
µs
Power Supply Rejection
±0.002%FSR/%
OUTPUTS
Output Voltage Ranges, Unipolar
0 to +5V, 0 to +10V
Output Voltage Ranges, Bipolar
±2.5V
±5V
±10V
Output Current
±5mA min.
Output Impedance
0.05 Ohm
POWER REQUIREMENTS
Power Supply Voltages
+15V, ±0.5V at 15mA
–15V, ±0.5V at 30mA
+5V, ±0.25V at 65mA
PHYSICAL ENVIRONMENTAL
Operating Temperature Range, Case
0°C to +70°C (BGC, BMC)
–55°C to +125°C (BMM, 883)
Storage Temperature Range
–65°C to +125°C
Package Type
24-pin DDIP
Weight
0.22 ounces (6.3 grams)
TECHNICAL NOTES
1. It is recommended that these converters be operated with
local supply bypass capacitors of 1
µF (tantalum type) at the
+15V, –15V and +5V supply pins. The capacitors should be
connected as close to the pins as possible. In high RFI
noise environments, these capacitors should be shunted
with 0.01
µF ceramic capacitors.
2. The analog, digital and power grounds should be separated
from each other as close as possible to pin 21 where they
all must come together.
3. The “load” control pin is a level-triggered input which causes
the register to hold data with a high input and transfer data
to the DAC with a low input.
4. A setup time of 50ns minimum must be allowed for the input
data. The DAC output voltage begins to change when the
register output changes.
5. If the reference output terminal (pin 24) is used, an
operational amplifier in non-inverting mode should be used
as a buffer. Current drawn from pin 24 should be limited to
±10
µA in order not to affect the T.C. of the reference
ABSOLUTE MAXIMUM RATINGS
Positive Supply, Pin 22
+18V
Negative Supply, Pin 14
–18V
Logic Supply, Pin 13
+5.25V
Digital Input Voltage, Pins 1–12 & 16
+5.5V
Output Current, Pin 15
±20mA
Lead Temperature (soldering, 10s)
300°C
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C and ±15V and +5V supplies unless otherwise noted.)
CALIBRATION PROCEDURE
Select the desired output voltage range and connect the
converter as shown in the Output Range Selection Table and
the Connection Diagrams. Refer to the Coding Tables.
Unipolar Operation
1. Zero Adjustment. Set the input digital code to 0000 0000
0000 and adjust the ZERO ADJ. potentiometer to give
0.0000V output.
2. Gain Adjustment. Set the input digital code to 1111 1111
1111 (straight binary) and adjust the GAIN ADJ. potentiom-
eter to give the full-scale output voltage shown in Table 1.
Bipolar Operation
1. Offset Adjustment. Set the digital input code to 0000 0000
0000 (offset binary) or 1000 0000 0000 (two’s complement)
and adjust the OFFSET ADJ. potentiometer to give the
negative full-scale output voltage shown in Table 2.
2. Gain Adjustment. Set the digital input code to 1111 1111
1111 (offset binary) or 0111 1111 1111 (two’s complement)
and adjust the GAIN ADJ. potentiometer to give the positive
full-scale output voltage shown in Table 2.
Footnotes:
➀ For two’s complement coding, order the "-2" model as described
in Ordering Information.
➁ Logic levels are the same as for data inputs.
➂ Initial errors are trimmable to zero. See Connection Diagram.
➃ FSR is full scale range and is 10V for 0 to +10V output range,
20V for ±10V output range, etc.
➄ By external pin connection.
➅ For ±12V, +5V operation, contact factory.
DATA IN
LOAD
REGISTER
OUTPUT TO
DAC
50nsec min.
Hold
Transfer
1
0
t
SETUP
50nsec min.
t
SETUP
60nsec
t
PLH
60nsec
t
PHL
ALL RISE AND FALL TIMES
≤ 10nsec
Figure 2. DAC-HK Timing


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