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CSD-1401MC 数据表(PDF) 1 Page - Murata Power Solutions Inc. |
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CSD-1401MC 数据表(HTML) 1 Page - Murata Power Solutions Inc. |
1 / 8 page 1 OFFSET ADJUST V1 2 OFFSET ADJUST I1 3 ANALOG INPUT 1 4 ANALOG INPUT 2 5 ANALOG GROUND 6 S/H1 OUT 7 S/H1 ROUT 8 S/H2 SUMMING NODE 9 OFFSET ADJUST V2 10 OFFSET ADJUST I2 11 S/H1 COMMAND 12 S/H2 COMMAND INPUT/OUTPUT CONNECTIONS 24 +15V ANALOG SUPPLY 23 ANALOG GROUND 22 V OUT 21 ANALOG GROUND 20 A/D CLOCK2 19 A/D CLOCK2 18 A/D CLOCK1 17 A/D CLOCK1 16 +5V DIGITAL SUPPLY 15 DIGITAL GROUND 14 ANALOG GROUND 13 –15V ANALOG SUPPLY FEATURES ••••• Use with 10 to 14-bit A/D converters ••••• 1.25 Megapixels/second minimum throughput (14 bits) ••••• ±10V input/output ranges, Gain = –1 ••••• Low noise, 200µVrms ••••• Two independent S/H amplifiers ••••• Gain matching between S/H's ••••• Offset adjustments for each S/H ••••• Four external A/D control lines ••••• Small package, 24-pin ceramic DDIP ••••• Low power, 700mW ••••• Low cost GENERAL DESCRIPTION The CDS-1401 is an application-specific, correlated double sampling (CDS) circuit designed for electronic-imaging applications that employ CCD’s (charge coupled devices) as their photodetector. The CDS-1401 has been optimized for use in digital video applications that employ 10 to 14-bit A/D converters. The low-noise CDS-1401 can accurately determine each pixel’s true video signal level by sequentially sampling the pixel’s offset signal and its video signal and subtracting the two. The result is that the consequences of residual charge, charge injection and low-frequency “kTC” noise on the CCD’s output floating capacitor are effectively eliminated. The CDS-1401 can also be used as a dual sample-hold amplifier in a data acquisition system. The CDS-1401 contains two sample-hold amplifiers and appropriate support/control circuitry. Features include independent offset-adjust capability for each S/H, adjustment for matching gain between the two S/H’s, and four control PIN FUNCTION PIN FUNCTION INNOVATION and EXCELLENCE ® ® Figure 1. CDS-1401 Functional Block Diagram lines for triggering the A/D converter used in conjunction with the CDS-1401. The CDS circuit’s “ping-pong” timing approach (the offset signal of the “n+1” pixel can be acquired while the video output of the “nth” pixel is being converted) guarantees a minimum throughput, in a 14-bit application, of 1.25MHz. In other words, the true video signal (minus offset) will be available (continued on page 4-5) CDS-1401 14-Bit, Fast-Settling Correlated Double Sampling Circuit S/H 2 OFFSET ADJUST V1 1 OFFSET ADJUST I1 2 ANALOG INPUT 1 3 S/H 1 OFFSET ADJUST V2 9 OFFSET ADJUST I2 10 ANALOG INPUT 2 4 S/H1 COMMAND 11 S/H2 COMMAND 12 5, 14, 21, 23 ANALOG GROUND 24 +15V SUPPLY 16 +5V DIGITAL SUPPLY 15 DIGITAL GROUND 7 S/H1 ROUT 8 S/H2 SUMMING NODE 22 V OUT 18 A/D CLOCK 1 6 S/H1 OUT OPTIONAL 17 A/D CLOCK 1 19 A/D CLOCK 2 20 A/D CLOCK 2 CH = 100pF 1kΩ 100 Ω 100kΩ 1kΩ CH = 100pF 100k Ω 1kΩ 900 Ω 1kΩ 13 –15V SUPPLY – + – + DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.) • Tel: (508) 339-3000 Fax: (508) 339-6356 • For immediate assistance (800) 233-2765 |
类似零件编号 - CSD-1401MC |
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类似说明 - CSD-1401MC |
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