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CDC921DLR 数据表(PDF) 3 Page - Texas Instruments |
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CDC921DLR 数据表(HTML) 3 Page - Texas Instruments |
3 / 17 page CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS623 –MAY 27, 1999 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION 3V66 [0–2] 21–23 O 3.3 V, Type 5, 66-MHz clock outputs 48MHz 27 O 3.3 V, Type 3, 48-MHz clock output APIC 46 O 2.5 V, Type 2, APIC clock output at 16.67 MHz CPU [0–2] 36, 37, 40 O 2.5 V, Type 1, CPU clock outputs CPU_DIV2 43 O 2.5 V, Type 1, CPU_DIV2 clock output GND 6, 14, 20, 26, 33, 35, 39, 42, 45, 48 Ground for PCI, 3V66, 48MHz, CPU, CPU_DIV2, APIC, REF [0–1] outputs and CORE PCI [0–9] 7, 8, 10–13, 15, 16, 18, 19 O 3.3 V, Type 5, 33-MHz PCI clock outputs PWR_DWN 32 I Power down for complete device with outputs forced low REF0, REF1 1, 2 O 3.3 V, Type 3, 14.318-MHz reference clock outputs SEL0, SEL1 29, 30 I LVTTL level logic select terminals for function selection SEL133/100 25 I LVTTL level logic select terminal for enabling 100/133 MHz SPREAD 31 I Disables SSC function VDD2.5V 38, 41, 44, 47 Power for CPU, CPU_DIV2, and APIC outputs VDD3.3V 3, 9, 17, 24, 28, 34 Power for the REF, PCI, 3V66, 48MHz outputs and CORE XIN 4 I Crystal input – 14.318 MHz XOUT 5 O Crystal output – 14.318 MHz |
类似零件编号 - CDC921DLR |
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类似说明 - CDC921DLR |
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