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CDC536DB 数据表(PDF) 1 Page - Texas Instruments |
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CDC536DB 数据表(HTML) 1 Page - Texas Instruments |
1 / 12 page CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS378F – APRIL 1994 – REVISED OCTOBER 1998 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Low-Output Skew for Clock-Distribution and Clock-Generation Applications D Operates at 3.3-V VCC D Distributes One Clock Input to Six Outputs D One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency D No External RC Network Required D External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input D Application for Synchronous DRAM, High-Speed Microprocessor D Negative-Edge-Triggered Clear for Half-Frequency Outputs D TTL-Compatible Inputs and Outputs D Outputs Drive 50-Ω Parallel-Terminated Transmission Lines D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D Distributed VCC and Ground Pins Reduce Switching Noise D Packaged in Plastic 28-Pin Shrink Small Outline Package description The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50-W transmission line. The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN. The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock. Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation. Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Copyright © 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. EPIC- ΙΙB is a trademark of Texas Instruments Incorporated. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVCC AGND CLKIN SEL OE GND 1Y1 VCC GND 1Y2 VCC GND 1Y3 VCC AVCC AGND FBIN TEST CLR VCC 2Y1 GND VCC 2Y2 GND VCC 2Y3 GND DB OR DL PACKAGE (TOP VIEW) |
类似零件编号 - CDC536DB |
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类似说明 - CDC536DB |
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