数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CDC516 数据表(PDF) 4 Page - Texas Instruments

Click here to check the latest version.
部件名 CDC516
功能描述  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Download  11 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDC516 数据表(HTML) 4 Page - Texas Instruments

  CDC516 Datasheet HTML 1Page - Texas Instruments CDC516 Datasheet HTML 2Page - Texas Instruments CDC516 Datasheet HTML 3Page - Texas Instruments CDC516 Datasheet HTML 4Page - Texas Instruments CDC516 Datasheet HTML 5Page - Texas Instruments CDC516 Datasheet HTML 6Page - Texas Instruments CDC516 Datasheet HTML 7Page - Texas Instruments CDC516 Datasheet HTML 8Page - Texas Instruments CDC516 Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 11 page
background image
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
TYPE
DESCRIPTION
CLK
12
I
Clock input. CLK provides the clock signal to be distributed by the CDC516 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
FBIN
37
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
1G
9
I
Output bank enable. 1G is the output enable for outputs 1Y(0:3). When 1G is low, outputs 1Y(0:3) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:3) are enabled and switch at the same
frequency as CLK.
2G
16
I
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic-low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
3G
33
I
Output bank enable. 3G is the output enable for outputs 3Y(0:3). When 3G is low, outputs 3Y(0:3) are
disabled to a logic-low state. When 3G is high, all outputs 3Y(0:3) are enabled and switch at the same
frequency as CLK.
4G
40
I
Output bank enable. 4G is the output enable for outputs 4Y(0:3). When 4G is low, outputs 4Y(0:3) are
disabled to a logic-low state. When 4G is high, all outputs 4Y(0:3) are enabled and switch at the same
frequency as CLK.
FBOUT
35
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
1Y(0:3)
2, 3, 6, 7
O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 1Y(0:3) are enabled via 1G.
These outputs can be disabled to a logic-low state by deasserting the 1G control input.
2Y(0:3)
18, 19, 22, 26
O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 2Y(0:3) are enabled via 2G.
These outputs can be disabled to a logic-low state by deasserting the 2G control input.
3Y(0:3)
31, 30, 27, 26
O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 3Y(0:3) are enabled via 3G.
These outputs can be disabled to a logic-low state by deasserting the 3G control input.
4Y(0:3)
47, 46, 43, 42
O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 4Y(0:3) are enabled via 4G.
These outputs can be disabled to a logic-low state by deasserting the 4G control input.
AVCC
11, 38
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, the PLL is
bypassed and CLK is buffered directly to the device outputs.
AGND
13, 14, 36
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
1, 8, 17, 24,
25, 32, 41, 48
Power
Power supply
GND
4, 5, 10, 15,
20, 21, 28, 29,
34, 39, 44, 45
Ground
Ground


类似零件编号 - CDC516

制造商部件名数据表功能描述
logo
Texas Instruments
CDC509 TI-CDC509 Datasheet
132Kb / 9P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC509 TI1-CDC509 Datasheet
612Kb / 13P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC509PW TI-CDC509PW Datasheet
132Kb / 9P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC509PWR TI1-CDC509PWR Datasheet
612Kb / 13P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC509PWRG4 TI1-CDC509PWRG4 Datasheet
612Kb / 13P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
More results

类似说明 - CDC516

制造商部件名数据表功能描述
logo
Texas Instruments
CDC2510 TI-CDC2510 Datasheet
131Kb / 9P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
logo
Hitachi Semiconductor
HD74CDC2510B HITACHI-HD74CDC2510B Datasheet
45Kb / 11P
   3.3-V Phase-lock Loop Clock Driver
logo
Texas Instruments
CDCF2509 TI1-CDCF2509_17 Datasheet
641Kb / 15P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2505 TI-CDCVF2505 Datasheet
207Kb / 10P
[Old version datasheet]   3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
CDC2509 TI-CDC2509 Datasheet
132Kb / 9P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509C TI-CDC2509C Datasheet
180Kb / 12P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510B TI-CDC2510B Datasheet
146Kb / 10P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510C TI-CDC2510C Datasheet
180Kb / 12P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC509 TI1-CDC509_15 Datasheet
612Kb / 13P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
logo
Hitachi Semiconductor
HD74CDC2509B HITACHI-HD74CDC2509B Datasheet
42Kb / 11P
   3.3-V Phase-lock Loop Clock Driver
logo
Texas Instruments
CDC2509B TI-CDC2509B Datasheet
147Kb / 10P
[Old version datasheet]   3.3-V PHASE-LOCK LOOP CLOCK DRIVER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com