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CDC2510BPWR 数据表(PDF) 1 Page - Texas Instruments

部件名 CDC2510BPWR
功能描述  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDC2510BPWR 数据表(HTML) 1 Page - Texas Instruments

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CDC2510B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS612 – SEPTEMBER 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Designed to Meet PC SDRAM Registered
DIMM Specification
D Spread Spectrum Clock Compatible
D Operating Frequency 25 MHz to 125 MHz
D tPhase Error Minus Jitter at 66MHz to
100MHz is
±150ps
D Jitter (pk – pk) at 66 MHz to 100 MHz is
±80ps
D Jitter (cyc – cyc) at 66 MHz to 100 MHz is
|100 ps|
D Available in Plastic 24-Pin TSSOP
D Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D Distributes One Clock Input to One Bank of
Ten Outputs
D Separate Output Enable for Each Output
Bank
D External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
D On-Chip Series Damping Resistors
D No External RC Network Required
D Operates at 3.3-V
description
The CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2510B operates at 3.3-V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510B does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510B requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDC2510B is characterized for operation from 0
°C to 70°C.
For application information refer to application reports
High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread
Spectrum Clocking (SSC) (literature number SCAA039).
Copyright
© 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CLK
AVCC
VCC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FBIN
1
2
3
4
5
6
7
8
9
10
11
12
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
G
FBOUT
24
23
22
21
20
19
18
17
16
15
14
13
PW PACKAGE
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