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MC-ACT-RSENC-VHDL 数据表(PDF) 3 Page - Actel Corporation |
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MC-ACT-RSENC-VHDL 数据表(HTML) 3 Page - Actel Corporation |
3 / 5 page Reed-Solomon Encoder Memec Design April 24, 2003 3 Optimized for MDS1029 FF ADD FF MULT FF ADD FF MULT FF ADD FF MULT FF ADD FF ADD FF MULT FF MULT IN_RS RS_CALC OUT_RS 0 1 REG REG REG REG REG REG REG Figure 2: Block Diagram Functional Description The Reed-Solomon encoder core is partitioned into modules as shown in Figure 2, and described below. All registers are driven by common clock (CLK), clock enable (CLKEN), and asynchronous reset (RST) signals. This provides ultimate flexibility in integration of the core into larger systems. The registers are clocked on the rising edge of CLK, enabled by a high on CLKEN, and asynchronously reset by a high on RST. The RS_CALC signal controls whether the core is calculating the parity (high) or shifting out the calculated parity (low). Logic external to the core is required to generate this control signal. This allows the user to vary the message block length as desired for shortened codes. The RS_CALC pin must be held at a low for 2t enabled clock cycles to ensure all parity register values are shifted out and the registers are cleared. FFADD Blocks perform modulo 2 addition of the input symbols. FFMULT Blocks perform a finite field multiplication, over the Galois field, of a constant and the input symbol. Timing Figure 3 shows a simple timing diagram of the RSENC interfaces for a Reed-Solomon block code of RS(204,188). MDS1030 IN_RS[7:0] RS_CALC CLK CLKEN OUT_RS[7:0] M187 M186 M0 M187 M186 P0 P1 M185 M184 P14 P15 M0 M1 M2 M3 M0 M1 Figure 3: RSENC Timing |
类似零件编号 - MC-ACT-RSENC-VHDL |
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类似说明 - MC-ACT-RSENC-VHDL |
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