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TC514COI 数据表(PDF) 9 Page - TelCom Semiconductor, Inc |
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TC514COI 数据表(HTML) 9 Page - TelCom Semiconductor, Inc |
9 / 17 page 3-27 TELCOM SEMICONDUCTOR, INC. 7 6 5 4 3 1 2 8 Figure 5. Comparator Output INTEGRATOR OUTPUT ZERO CROSSING COMPARATOR OUTPUT REFERENCE DEINTEGRATE SIGNAL INTEGRATE INTEGRATOR OUTPUT ZERO CROSSING COMPARATOR OUTPUT REFERENCE DEINTEGRATE SIGNAL INTEGRATE B. Negative Input Signal A. Positive Input Signal Comparator Output By monitoring the comparator output during the fixed signal integrate time, the input signal polarity can be deter- mined by the microprocessor controlling the conversion. The comparator output is HIGH for positive signals and LOW for negative signals during the signal-integrate phase (see timing diagram). During the reference deintegrate phase, the comparator output will make a HIGH-to-LOW transition as the integrator output ramp crosses zero. The transition is used to signal the processor that the conversion is complete. The internal comparator delay is 2 µsec, typically. Figure 5 shows the comparator output for large positive and nega- tive signal inputs. For signal inputs at or near zero volts, however, the integrator swing is very small. If common- mode noise is present, the comparator can switch several times during the beginning of the signal-integrate period. To ensure that the polarity reading is correct, the comparator output should be read and stored at the end of the signal integrate phase. The comparator output is undefined during the Auto- Zero Phase and is used to time the Integrator Output Zero phase. (See Integrator Output Zero Phase of System Timing section). PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514 |
类似零件编号 - TC514COI |
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类似说明 - TC514COI |
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