STC5230 datasheet(5/48 Pages) CONNOR-WINFIELD

部件名	STC5230

功能描述	Synchronous Clock for SETS

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制造商	CONNOR-WINFIELD [Connor-Winfield Corporation]

网页	http://www.conwin.com

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5 / 48 page

Data Sheet #: TM102

Page 5 of 48

Rev: P01

Date: August 22, 2007

STC5230

Synchronous Clock for SETS

Data Sheet

Preliminary

STC5230 Pin Description

All I/O is LVCMOS, except for CLK0 and CLK8, which are LVPECL.

Table 1: Pin Description

Pin Name

Pin #

I/O

Description

Vdd33

6,22,31,

44,59,61,

69,80,

87,97

3.3V power input

Vdd18

9,18,27,

38,47,53,

60,65,84,

92

1.8V power input

Vss

3,13,15,

20,29,35,

41,56,64,

67,71,78,

82,88,95

Digital ground

AVdd18

1, 76

1.8V analog power input

AVss

75, 100

Analog ground

TRST

94

I

JTAG boundary scan reset, active low

TCK

93

I

JTAG boundary scan clock

TMS

91

I

JTAG boundary scan mode selection

TDI

90

I

JTAG boundary scan data input

TDO

89

O

JTAG boundary scan data output

RESET

30

I

Active low to reset the chip

MCLK

99

I

Master clock input, 20 MHz

SPI_CS

45

I

SPI bus chip select (CS)

SPI_SCK

46

I

SPI bus clock input (SCLK)

SPI_SDI

50

I

SPI bus data input (SDI)

SPI_SDO

51

O

SPI bus data output (SDO)

EEP_SO

37

I/O

Optional external EEPROM SO

EEP_SI

36

I/O

Optional external EEPROM SI

EEP_SCK

34

I/O

Optional external EEPROM SCK

EEP_CS

33

I/O

Optional external EEPROM CS

EVENT_INTR

32

O

event interrupt

REF1

2

I

Reference input 1

REF2

4

I

Reference input 2

REF3

5

I

Reference input 3

REF4

8

I

Reference input 4

REF5

10

I

Reference input 5

REF6

12

I

Reference input 6

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