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STFLWARP20 数据表(PDF) 7 Page - STMicroelectronics |
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STFLWARP20 数据表(HTML) 7 Page - STMicroelectronics |
7 / 28 page ON-LINE MODE In On-line mode (see figure 7) W.A.R.P.2.0 is en- abled to elaborate input values and calculate out- puts according to the fuzzy rules stored into the microprogram. W.A.R.P.2.0 reads the input values one a time in the inp ut da ta bus using the RD/READY signals. If the processor is working in SLAVE mode (see register bench description in table 5) the user has to provide the inputs with their identificationnumbers (by means of SIS0-SIS2), so it is possible to provide inputs in any order. In SLAVE mode it i s a ls o po ssib le to f orce W.A.R.P.2.0 to start the elaboration phase (by means of LASTIN) without providing all inputs, for instance when input variables change with different speed. In this case the outputs that have not be provided in this cycle, but sampled in the previous ones, are recovered from the internal buffers. When all inputs are given or a LASTIN signal is given, the elaboration phase starts. The elabora- tion phase is divided in two main parts. During the first one the input values are read and the corre- sponding ALPHA values (activation levels) are cal- culated. In the second part the computation of the fuzzy rules and the defuzzification are imple- mented. W.A.R.P.2.0 acquires each input in 8 clock pulses (min). Since the acquisition phase is performed by the user by means of the handshaking signals, 8 clock pulses per input are referred to the most efficient case. In figure 6 are shown the perform- 0 6 4 1 28 192 256 0 2.0 00 4.0 00 6.0 00 8.0 00 Num b e r of Ru le s Num b e r of Clo ck Pu ls e s Numbe r of Inputs = 8 Figure 6. W.A.R.P.2.0 performances ances in case of 8 inputs. If you are using less inputs you have to subtract 8 clock pulses for each of them. The elaboration time for rule requires 32 clock pulses. For instance if W.A.R.P.2.0 is working at a fre- quency of 40 MHz (25ns period) with 8 inputs and 128 rules globally (for all outputs) the time required to provide all outputs is 4000clkp*25ns = 100 µs. O n-line Ph a se Ma ster (”MASTER” s e t in th e regi ster ben ch) O n-line Ph a se Ena ble OFL=LOW Input s Acquisition with Hands ha king Sign als (RD/READY) CHIP PRESET En d of Acquisition Ph a se S tart Elaboration Pha se Elaboration P h a se O utputs Gen eration DS=HIGH On-line Ph a se Sl ave (”SLAVE” set in the register be nc h) O n-line Ph a se Ena ble OFL=LOW Acquisition with Hands haking by s p ecifying which inputs is on the input bu s by m e an s of SIS0-SIS 2 CHIP PRESET End of Acquisition Ph as e S tart Elabora tion Pha se Elabora tion P h ase Outputs Ge n eration DS=HIGH Last Input h as b een give n LASTIN=HIGH Figure 7. On-Line phase 7/28 W.A.R.P.2.0 |
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