数据搜索系统,热门电子元器件搜索 |
|
CS2100-CP 数据表(PDF) 2 Page - Cirrus Logic |
|
CS2100-CP 数据表(HTML) 2 Page - Cirrus Logic |
2 / 32 page CS2100-CP 2 DS840PP1 TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ................................................... 8 CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ................................................. 9 4. ARCHITECTURE OVERVIEW ............................................................................................................. 10 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 10 4.2 Hybrid Analog-Digital Phase Locked Loop ....................................................................................10 5. APPLICATIONS ................................................................................................................................... 12 5.1 Timing Reference Clock Input ........................................................................................................ 12 5.1.1 Internal Timing Reference Clock Divider ............................................................................... 12 5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 12 5.1.3 External Reference Clock (REF_CLK) .................................................................................. 13 5.2 Frequency Reference Clock Input, CLK_IN ................................................................................... 13 5.2.1 CLK_IN Frequency Detector ................................................................................................. 13 5.2.2 CLK_IN Skipping Mode ......................................................................................................... 13 5.2.3 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 15 5.3 Output to Input Frequency Ratio Configuration ............................................................................. 16 5.3.1 User Defined Ratio (RUD) ..................................................................................................... 16 5.3.2 Manual Ratio Modifier (R-Mod) ............................................................................................. 17 5.3.3 Automatic Ratio Modifier (Auto R-Mod) ................................................................................. 17 5.3.4 Effective Ratio (REFF) .......................................................................................................... 18 5.3.5 Ratio Configuration Summary ............................................................................................... 19 5.4 PLL Clock Output ........................................................................................................................... 20 5.5 Auxiliary Output .............................................................................................................................. 20 5.6 Clock Output Stability Considerations ............................................................................................ 21 5.6.1 Output Switching ................................................................................................................... 21 5.6.2 PLL Unlock Conditions .......................................................................................................... 21 6. SPI / I²C CONTROL PORT ................................................................................................................... 22 6.1 SPI Control ..................................................................................................................................... 22 6.2 I²C Control ...................................................................................................................................... 22 6.3 Memory Address Pointer ............................................................................................................... 24 6.3.1 Map Auto Increment .............................................................................................................. 24 7. REGISTER QUICK REFERENCE ........................................................................................................ 24 8. REGISTER DESCRIPTIONS ................................................................................................................ 25 8.1 Device I.D. and Revision (Address 01h) ....................................................................................... 25 8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 25 8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 25 8.2 Device Control (Address 02h) ........................................................................................................ 25 8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 25 8.2.2 PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only .................................................. 25 8.2.3 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 26 8.2.4 Auxiliary Output Disable (AuxOutDis) ................................................................................... 26 8.2.5 PLL Clock Output Disable (ClkOutDis) .................................................................................. 26 8.3 Device Configuration 1 (Address 03h) ........................................................................................... 26 8.3.1 R-Mod Selection (RModSel[2:0]) ...........................................................................................26 8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 27 8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 27 |
类似零件编号 - CS2100-CP |
|
类似说明 - CS2100-CP |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |