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74HCT4852PW 数据表(PDF) 11 Page - NXP Semiconductors |
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74HCT4852PW 数据表(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 74HC_HCT4852_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 September 2008 11 of 20 NXP Semiconductors 74HC4852; 74HCT4852 4-channel analog MUX/DEMUX with injection-current effect control [1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] CPD is used to determine the dynamic power dissipation (PD in µW): PD =CPD × VCC2 × fi + ∑{(CL +Csw) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; ∑{(C L +Csw) × VCC 2 × f o} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. 12. Waveforms 74HCT4852 tpd propagation delay nZ, nYn to nYn, nZ; see Figure 10 [1] VCC = 4.5 V 1.6 3.5 11.5 1.1 12.5 1.1 13.5 ns Sn to nZ, nYn; see Figure 11 [1] VCC = 4.5 V 3.2 7.6 13 2.3 15 1.6 17 ns ten enable time E to nZ, nYn; see Figure 12 [2] VCC = 4.5 V 4.2 8.3 25 3.0 30 3.0 35 ns tdis disable time E to nZ, nYn; see Figure 12 [3] VCC = 4.5 V 28.5 61.8 80 28.2 90 28.0 100 ns CPD power dissipation capacitance per channel; see Figure 13 [4] VCC = 5.0 V - 47 - - - - - pF Table 9. Dynamic characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V); for load circuit see Figure 14. Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max Fig 10. Input (nZ, nYn) to output (nYn, nZ) propagation delays 001aah578 VCC nZ or nYn input nYn or nZ output tPLH 0.5VCC 0.5VCC tPHL GND VCC GND |
类似零件编号 - 74HCT4852PW |
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类似说明 - 74HCT4852PW |
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