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AD7682 数据表(PDF) 7 Page - Analog Devices |
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AD7682 数据表(HTML) 7 Page - Analog Devices |
7 / 28 page AD7949 Rev. A | Page 7 of 28 VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 4. 1 Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available tCONV 3.2 μs Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 5 μs CNV Pulse Width tCNVH 10 ns Data Write/Read During Conversion tDATA 1.0 μs SCK Period tSCK 25 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 37 ns CNV Low to SDO D15 MSB Valid tEN VIO Above 3 V 21 ns VIO Above 2.7 V 27 ns VIO Above 2.3 V 35 ns CNV High or Last SCK Falling Edge to SDO High Impedance tDIS 50 ns CNV Low to SCK Rising Edge tCLSCK 10 ns SDI Valid Setup Time from SCK Falling Edge tSDIN 5 ns SDI Valid Hold Time from SCK Falling Edge tHDIN 5 ns 1 See Figure 2 and Figure 3 for load conditions. IOL 500µA 500µA IOH 1.4V TOSDO CL 50pF Figure 2. Load Circuit for Digital Interface Timing 30% VIO 70% VIO 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2 2V OR VIO – 0.5V1 tDELAY tDELAY 1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Voltage Levels for Timing |
类似零件编号 - AD7682 |
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类似说明 - AD7682 |
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