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AD5734RBREZ 数据表(PDF) 8 Page - Analog Devices |
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AD5734RBREZ 数据表(HTML) 8 Page - Analog Devices |
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8 / 32 page  AD5724R/AD5734R/AD5754R Preliminary Technical Data Rev. PrC | Page 8 of 32 TIMING CHARACTERISTICS AVDD = 4.5 V to 16.5 V, AVSS = −4.5 V to −16.5 V / 0V, GND = 0 V, REFIN = 2.5 V external, DVCC = 2.7 V to 5.5 V, RLOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 13 ns min SCLK falling edge to SYNC rising edge t6 100 ns min Minimum SYNC high time (write mode) t7 5 ns min Data setup time t8 0 ns min Data hold time t9 20 ns min LDAC falling edge to SYNC falling edge t10 20 ns min SYNC rising edge to LDAC falling edge t11 20 ns min LDAC pulse width low t12 1.5 µs max LDAC falling edge to DAC output response time t13 10 µs max DAC output settling time t14 1.5 µs max SYNC rising edge to output response time (LDAC = 0) t15 20 ns min CLR pulse width low t16 2.5 µs max CLR pulse activation time t174 13 ns min SYNC rising edge to SCLK falling edge t184 40 ns max SCLK rising edge to SDO valid (CL SDO5 = 15 pF) t19 200 ns min Minimum SYNC high time (readback/daisy-chain mode) 1 Guaranteed by characterization. Not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 Daisy-chain and Readback mode. 5 CL SDO = Capacitive load on SDO output. |
类似零件编号 - AD5734RBREZ |
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类似说明 - AD5734RBREZ |
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