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AD5724RBREZ-REEL7 数据表(PDF) 5 Page - Analog Devices |
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AD5724RBREZ-REEL7 数据表(HTML) 5 Page - Analog Devices |
5 / 32 page Preliminary Technical Data AD5724R/AD5734R/AD5754R Rev. PrC | Page 5 of 32 Parameter Value Unit Test Conditions/Comments OUTPUT CHARACTERISTICS2 Output Voltage Range ±10.8 V min to V max AVDD/AVSS = ±11.7 V min , REFIN = +2.5 V ±12 V min to V max AVDD/AVSS = ±12.9 V min, REFIN = +3 V Headroom 0.9 V max 0.5 V typ Output Voltage TC ±8 ppm FSR/°C max Output Voltage Drift vs. Time ±12 ppm FSR/500 hr typ ±15 ppm FSR/1000 hr typ Short-Circuit Current 20 mA typ Load 2 kΩ min For specified performance Capacitive Load Stability 4000 pF max DC Output Impedance 0.5 Ω typ DIGITAL INPUTS2 DVCC = 2.7 V to 5.5 V, JEDEC compliant VIH, Input High Voltage 2 V min VIL, Input Low Voltage 0.8 V max Input Current ±1 µA max Per pin Pin Capacitance 5 pF typ Per pin DIGITAL OUTPUTS (SDO) 2 VOL, Output Low Voltage 0.4 V max DVCC = 5 V ± 10%, sinking 200 µA VOH, Output High Voltage DVCC − 1 V min DVCC = 5 V ± 10%, sourcing 200 µA VOL, Output Low Voltage 0.4 V max DVCC = 2.7 V to 3.6 V, sinking 200 µA VOH, Output High Voltage DVCC − 0.5 V min DVCC = 2.7 V to 3.6 V, sourcing 200 µA High Impedance Leakage Current ±1 µA max High Impedance Output Capacitance 5 pF typ POWER REQUIREMENTS AVDD 4.5 to 16.5 V min to V max AVSS -4.5 to -16.5 V min to V max DVCC 2.7 to 5.5 V min to V max Power Supply Sensitivity2 ∆VOUT/∆ΑVDD −75 dB typ 200mV sine wave superimposed on AVSS/AVDD @ 50/60 Hz AIDD 2 mA/channel max Outputs unloaded AISS 1.5 mA/channel max Outputs unloaded DICC 1 µA max VIH = DVCC, VIL = GND, 0.5 µA typ Power Dissipation TBD mW typ ±12 V operation, outputs unloaded Power-Down Currents All DAC channels and internal reference powered-down AIDD 80 µA typ AISS TBD µA typ DICC TBD µA typ 1 For specified performance minimum headroom requirement is 0.9V 2 Guaranteed by characterization. Not production tested. |
类似零件编号 - AD5724RBREZ-REEL7 |
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类似说明 - AD5724RBREZ-REEL7 |
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