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AD5724AREZ-REEL7 数据表(PDF) 5 Page - Analog Devices |
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AD5724AREZ-REEL7 数据表(HTML) 5 Page - Analog Devices |
5 / 32 page AD5724/AD5734/AD5754 Rev. 0 | Page 5 of 32 AC PERFORMANCE CHARACTERISTICS AVDD = 4.5 V1 to 16.5 V; AVSS = −4.5 V1 to −16.5 V, or 0 V; GND = 0 V; REFIN= 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD = 200 pF; all specifications TMIN to TMAX. Table 2. A, B Version Parameter2 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 10 12 μs 20 V step to ±0.03% FSR 7.5 8.5 μs 10 V step to ±0.03% FSR 5 μs 512 LSB step settling (16-bit resolution) Slew Rate 3.5 V/μs Digital-to-Analog Glitch Energy 13 nV-sec Glitch Impulse Peak Amplitude 35 mV Digital Crosstalk 10 nV-sec DAC-to-DAC Crosstalk 10 nV-sec Digital Feedthrough 0.6 nV-sec Output Noise 0.1 Hz to 10 Hz Bandwidth) 15 μV p-p 0x8000 DAC code 100 kHz Bandwidth 80 μV rms Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code 1 For specified performance, maximum headroom requirement is 0.9 V. 2 Guaranteed by design and characterization. Not production tested. TIMING CHARACTERISTICS AVDD = 4.5 V to 16.5 V; AVSS = −4.5 V to −16.5 V, or 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2, 3 Limit at tMIN, tMAX Unit Description t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 13 ns min SCLK falling edge to SYNC rising edge t6 100 ns min Minimum SYNC high time (write mode) t7 5 ns min Data setup time t8 0 ns min Data hold time t9 20 ns min LDAC falling edge to SYNC falling edge t10 20 ns min SYNC rising edge to LDAC falling edge t11 20 ns min LDAC pulse width low t12 10 μs typ DAC output settling time t13 20 ns min CLR pulse width low t14 2.5 μs max CLR pulse activation time t154 13 ns min SYNC rising edge to SCLK rising edge t164 40 ns max SCLK rising edge to SDO valid (CL SDO5 = 15 pF) t17 200 ns min Minimum SYNC high time (readback/daisy-chain mode) 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 Daisy-chain and readback mode. 5 CL SDO = capacitive load on SDO output. |
类似零件编号 - AD5724AREZ-REEL7 |
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类似说明 - AD5724AREZ-REEL7 |
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