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AD5754 数据表(PDF) 4 Page - Analog Devices |
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AD5754 数据表(HTML) 4 Page - Analog Devices |
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4 / 32 page  AD5724/AD5734/AD5754 Rev. 0 | Page 4 of 32 Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL INPUTS3 DVCC = 2.7 V to 5.5 V, JEDEC compliant Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current ±1 μA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS (SDO)3 Output Low Voltage, VOL 0.4 V DVCC = 5 V ± 10%, sinking 200 μA Output High Voltage, VOH DVCC − 1 V DVCC = 5 V ± 10%, sourcing 200 μA Output Low Voltage, VOL 0.4 V DVCC = 2.7 V to 3.6 V, sinking 200 μA Output High Voltage, VOH DVCC − 0.5 V DVCC = 2.7 V to 3.6 V, sourcing 200 μA High Impedance Leakage Current −1 +1 μA High Impedance Output Capacitance 5 pF POWER REQUIREMENTS AVDD 4.5 16.5 V AVSS −4.5 −16.5 V DVCC 2.7 5.5 V Power Supply Sensitivity3 ∆VOUT/∆ΑVDD −65 dB AIDD 2.5 mA/channel Outputs unloaded 1.75 mA/channel AVSS = 0 V, outputs unloaded AISS 2.2 mA/channel Outputs unloaded DICC 0.5 3 μA VIH = DVCC, VIL = GND Power Dissipation 310 mW ±16.5 V operation, outputs unloaded 115 mW 16.5 V operation, AVSS = 0 V, outputs unloaded Power-Down Currents AIDD 40 μA AISS 40 μA DICC 300 nA 1 For specified performance, maximum headroom requirement is 0.9 V. 2 INL is measured from Code 512, Code 128, and Code 32 for the AD5754, the AD5734, and the AD5724, respectively. 3 Guaranteed by characterization; not production tested. |
类似零件编号 - AD5754 |
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类似说明 - AD5754 |
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