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SN74AUP2G08RSER 数据表(PDF) 2 Page - Texas Instruments |
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SN74AUP2G08RSER 数据表(HTML) 2 Page - Texas Instruments |
2 / 15 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) This dual 2-input positive-AND gate performs the Boolean function Y + A • B or Y + A ) B in positive logic. 1A 1 2 7 1B 1Y 2A 5 6 3 2B 2Y SN74AUP2G08 LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE SCES681A – JANUARY 2008 – REVISED JANUARY 2008 NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE(1)(2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3) NanoFree™ – WCSP (DSBGA) Reel of 3000 SN74AUP2G08YFPR _ _ _ HE_ 0.23-mm Large Bump – YFP NanoFree™ – WCSP (DSBGA) Reel of 3000 SN74AUP2G08YZPR _ _ _ HE_ –40 °C to 85°C 0.23-mm Large Bump – YZP (Pb-free) QFN – RSE Reel of 3000 SN74AUP2G08RSER HE VSSOP – DCU Reel of 3000 SN74AUP2G08DCUR H08_ (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (3) YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). DCU – The actual top-side marking has one additional character to denote assembly/test site. FUNCTION TABLE INPUTS OUTPUT Y A B L L L L H L H L L H H H LOGIC DIAGRAM (POSITIVE LOGIC) Pin numbers shown are for DCU, YFP, and YZP packages. 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G08 |
类似零件编号 - SN74AUP2G08RSER |
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类似说明 - SN74AUP2G08RSER |
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