© 2006 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FIN324C Rev. 1.1.2

7

Master/Slave READ Transactions

Read transactions have two phases: The Read-Control

Phase, where CNTL[5:0], R/W, CKSEL are transmitted

to the deserializer; and the Read-Data Phase, where

the DP[17:0] signals of the slave are read and

transmitted back to the master device. The slave device

generates its own strobe signal for latching in the data.

Slave data must be valid prior to the WCLKn signal

going HIGH.

Master Serializer Operation (Read Control Phase)

When the R/W signal is asserted HIGH and the

STROBE signal transitions LOW, the Read-Control

Phase of the read cycle is initiated. The R/W signal

must not transition until the READ cycle completes. For

a READ transaction, only eight control signals are

captured. The 18 DP bits are ignored during the READ

operation. The following sequence must occur for data

to be serialized properly:

1. CPU selects input strobe source (CKSEL=0 or 1).

2. CPU sends signals (R/W=1, CKSEL, CNTL[5:0]).

3. CPU sends LOW STROBE signal.

Slave Deserializer Operation (Read-Control Phase)

1. Captures data from serial transfer.

2. Internally decodes that this is a READ transaction.

3. Outputs control signals and prepares DP pins to

accept data.

4. Outputs falling edge of WCLK pulse.

Slave Serializer Read Operation (Read-Data Phase)

The slave serializer is enabled on the tail end of the

Read-Control Phase of operation. The operation of the

serializer is identical to the master serialization except

that the strobe signal is generated internally and only

the data bits DP[17:0] are captured.

1. Display device outputs data onto DP bus on falling

edge of WCLK.

2. Captures parallel data on generated rising edge of

WCLK signal.

3. Serializes data stream.

Master Deserializer Read Operation (Read-Data Phase):

1. Receives valid serial stream.

2. Outputs data DP[17:0].

3. CPU asserts rising edge of strobe signal to capture data.

SPI WRITE transaction

SPI mode is activated by asserting the PAR/SPI signal

low on both the master and slave device. A SPI write is

only performed when CKSEL=0. During a SPI

transaction, SCLK must be connected to CNTL[5] and is

the strobe source for serialization. SDAT is on CNTL[4]

and all of the remaining control signals and STRB0 are

serialized. STRB0 should be connected to the SPI

mode chip select.

On the rising edge of SCLK, all eight control signals

(CNTL[5:0], R/W, CKSEL) are captured and serialized.

The data signals are not sent. The deserializer captures the

serial stream and outputs it to the parallel port.

As shown in Table 2, SDAT and SCLK are output on

multiple pins. The DP[7] and DP[6] connections can be

used for displays with dual-mode operation and the

data pins are multiplexed with the SPI signals. CNTL[5]

and CNTL[4] signals can be used when the signals are

not multiplexed.