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STPCELITE 数据表(PDF) 11 Page - STMicroelectronics |
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STPCELITE 数据表(HTML) 11 Page - STMicroelectronics |
11 / 87 page PIN DESCRIPTION Release 1.3 - January 29, 2002 11/87 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 2. PIN DESCRIPTION 2.1. INTRODUCTION The STPC Elite integrates most of the functionalities of the PC architecture. As a result, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC Elite. This offers improved performance due to the tight coupling of the processor core and these peripherals. As a result many of the external pin connections are made directly to the on-chip peripheral functions. Figure 2-1 shows the STPC Elite external interfaces. It defines the main buses and their function. Table 2-1 describes the physical implementation listing signals type and their functionality. Table 2-2 provides a full pin listing and description of pins. Table 2-7 provides a full listing of pin locations of the STPC Elite package by physical connection. Note: Several interface pins are multiplexed with other functions, refer to Table 2-4 and Table 2-5 for further details Table 2-1. Signal Description Group name Qty Basic Clocks reset & Xtal 6 Memory Interface 96 PCI interface 56 ISA 79 90 IDE 34 Local Bus 50 Grounds 69 VDD 22 Miscellaneous 8 GPIO 16 Unconnected 25 Total Pin Count 388 Figure 2-1. STPC Elite External Interfaces SOUTH NORTH PCI x86 SDRAM I/F SYS ISA/IDE/LB 96 56 6 90 STPC Elite |
类似零件编号 - STPCELITE |
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类似说明 - STPCELITE |
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