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STPCCONSUMER 数据表(PDF) 1 Page - STMicroelectronics

部件名 STPCCONSUMER
功能描述  PC Compatible Embeded Microprocessor
Download  51 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPCCONSUMER 数据表(HTML) 1 Page - STMicroelectronics

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®
STPC CONSUMER
PC Compatible Embeded Microprocessor
1/51
8/2/00
Issue 1.2
Figure 1. Logic Diagram
s
POWERFUL X86 PROCESSOR
s
64-BIT BUS ARCHITECTURE
s
64-BIT DRAM CONTROLLER
s
SVGA GRAPHICS CONTROLLER
s
UMA ARCHITECTURE
s
VIDEO SCALER
s
DIGITAL PAL/NTSC ENCODER
s
VIDEO INPUT PORT
s
CRT CONTROLLER
s
135MHz RAMDAC
s
3 LINE FLICKER FILTER
s
SCAN CONVERTER
s
PCI MASTER / SLAVE / ARBITER CTRL
s
ISA MASTER/SLAVE INTERFACE
s
IDE CONTROLLER
s
DMA CONTROLLER
s
INTERRUPT CONTROLLER
s
TIMER / COUNTERS
s
POWER MANAGEMENT
STPC CONSUMER OVERVIEW
The STPC Consumer integrates a standard 5th
generation x86 core, a DRAM controller, a graph-
ics subsystem, a video pipeline and support logic
including PCI, ISA and IDE controllers to provide a
single Consumer orientated PC compatible sub-
system on a single device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
Extra facilities are implemented to handle video
streams. Features include smooth scaling and
color space conversion of the video input stream
and mixing with graphics data. The chip also in-
cludes a built-in digital TV encoder and anti-flicker
filters that allow stable, high-quality display on
standard PAL or NTSC television sets without ad-
ditional components.
The STPC Consumer is packaged in a 388 Plastic
Ball Grid Array (PBGA).
PBGA388
x86
Core
Host I/F
DRAM
CTRL
VIP
PCI
m/s
PCI BUS
ISA
m/s
EIDE
PCI
m/s
ISA BUS
CRTC
H W C ursor
Monitor
TV Output
SYNC Output
C olor Space
C onverter
Color
Key
Chroma
Key
Video
pipeline
CCIR Input
EIDE
2D
SVGA
AntiFlicker
IPC
D igital
PAL/
NTSC


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