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LFXP6E-5FN256C 数据表(PDF) 5 Page - Lattice Semiconductor |
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LFXP6E-5FN256C 数据表(HTML) 5 Page - Lattice Semiconductor |
5 / 130 page 2-2 Architecture Lattice Semiconductor LatticeXP Family Data Sheet Figure 2-1. LatticeXP Top Level Block Diagram PFU and PFF Blocks The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec- tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-2. PFU Diagram Programmable I/O Cell (PIC) includes sysIO Interface Non-volatile Memory sysCONFIG Programming Port (includes dedicated and dual use pins) Programmable Functional Unit (PFU) sysCLOCK PLL PFF (PFU without RAM) JTAG Port sysMEM Embedded Block RAM (EBR) Slice 0 LUT4 & CARRY LUT4 & CARRY FF/ Latch D FF/ Latch D Slice 1 LUT4 & CARRY LUT4 & CARRY Slice 2 LUT4 & CARRY LUT4 & CARRY From Routing To Routing Slice 3 LUT4 & CARRY LUT4 & CARRY FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D |
类似零件编号 - LFXP6E-5FN256C |
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类似说明 - LFXP6E-5FN256C |
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