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LFXP3E-3T100I 数据表(PDF) 8 Page - Lattice Semiconductor |
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LFXP3E-3T100I 数据表(HTML) 8 Page - Lattice Semiconductor |
8 / 130 page 2-5 Architecture Lattice Semiconductor LatticeXP Family Data Sheet The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-4 shows the dis- tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions as the read-write port. The other companion Slice supports the read-only port. For more information on RAM mode in LatticeXP devices, please see details of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required for Implementing Distributed RAM Figure 2-4. Distributed Memory Primitives ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. PFU Modes of Operation Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the functionality possible at the PFU level. SPR16x2 DPR16x2 Number of Slices 1 2 Note: SPR = Single Port RAM, DPR = Dual Port RAM DO1 DO0 DI0 DI1 AD0 AD1 AD2 AD3 WRE CK DO0 AD0 AD1 AD2 AD3 DPR16x2 SPR16x2 ROM16x1 RDO1 RDO0 DI0 DI1 WCK WRE WDO1 WDO0 WAD0 WAD1 WAD2 WAD3 RAD0 RAD1 RAD2 RAD3 |
类似零件编号 - LFXP3E-3T100I |
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类似说明 - LFXP3E-3T100I |
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