数据搜索系统,热门电子元器件搜索 |
|
LC4256ZE7TN100IES 数据表(PDF) 11 Page - Lattice Semiconductor |
|
LC4256ZE7TN100IES 数据表(HTML) 11 Page - Lattice Semiconductor |
11 / 54 page Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 11 Figure 9. Power Guard All the I/O pins in a block share a common Power Guard Enable signal. For a block of I/Os, this signal is called a Block Input Enable (BIE) signal. BIE can be internally generated using MC logic, or could come from external sources using one of the user I/O or input pins. Any I/O pin in the block can be programmed to ignore the BIE signal. Thus, the feature can be enabled or disabled on a pin-by-pin basis. Figure 10 shows Power Guard and BIE across multiple I/Os in a block that has eight I/Os. Figure 10. Power Guard and BIE in a Block with 8 I/Os 0 1 E Q D Power Guard Power Guard To Macrocell I/O 0 I/O 1 I/O 7 To GRP 0 1 To Macrocell To GRP To Macrocell To GRP Block Input Enable (BIE) From Block PT. The Block PT is part of the block AND Array, and can be driven by signals from the GRP. Power Guard Power Guard 0 1 0 1 |
类似零件编号 - LC4256ZE7TN100IES |
|
类似说明 - LC4256ZE7TN100IES |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |