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M40Z300MH1F 数据表(PDF) 10 Page - STMicroelectronics |
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M40Z300MH1F 数据表(HTML) 10 Page - STMicroelectronics |
10 / 25 page Operation M40Z300, M40Z300W 10/25 2.1 Two to four decode The M40Z300/W includes a 2 input (A, B) decoder which allows the control of up to 4 independent SRAMs. The Truth Table for these inputs is shown in Table 2. Table 2. Truth table Figure 6. Address-decode time Note: During system design, compliance with the SRAM timing parameters must comprehend the propagation delay between E1CON - E4CON. 2.2 Data retention lifetime calculation Most low power SRAMs on the market today can be used with the M40Z300/W NVRAM SUPERVISOR. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40Z300/W and SRAMs to be “Don't Care” once VCC falls below VPFD(min). The SRAM should also guarantee data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the IBAT value of the M40Z300/W to determine the total current requirements for data retention. The available Inputs Outputs E BA E1CON E2CON E3CON E4CON HX XH H H H LL LL H H H LL H H L H H LHL H HLH L HHHH H L AI02551 A, B E E1CON - E4CON tAS tEDH tEDL |
类似零件编号 - M40Z300MH1F |
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类似说明 - M40Z300MH1F |
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