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74AUPG04DTR 数据表(PDF) 1 Page - STMicroelectronics |
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74AUPG04DTR 数据表(HTML) 1 Page - STMicroelectronics |
1 / 18 page March 2008 Rev 1 1/18 18 74AUP1G04 Low power single inverter gate Features ■ High speed: tPD = 4.3 ns (max.) at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: VCC (opr) = 1.2 to 3.6 V ■ Low power dissipation: ICC = 1 µA (max.) at TA = 85 °C ■ Latch-up performance exceeds 300 mA (JESD 78, Class II) ■ ESD performance: – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Applications ■ Mobile phones ■ Personal digital assistants (PDAs) Description The 74AUP1G04 is a low voltage CMOS single inverter gate fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.2 to 3.6 V operations and low power and low noise applications. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2kV ESD immunity and transient excess voltage. DFN6L SOT-665 Table 1. Device summary Order code Package Packing 74AUPG04DTR DFN6L (1.2 x 1 mm) Tape and reel 74AUPG04GTR SOT-665 (1.6 x 1.6 mm) Tape and reel www.st.com |
类似零件编号 - 74AUPG04DTR |
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类似说明 - 74AUPG04DTR |
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