STE100 datasheet(11/66 Pages) STMICROELECTRONICS

部件名	STE100

功能描述	PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

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制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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STE10/100

0

CIOSA

Command I/O Space Access

0: enable the I/O space access ability.

1: disable the I/O space access ability.

0

R/W

R/W: Read and Write able. RO: Read able only.

CR2(offset = 08h), CC - Class Code and Revision Number

31~24

BCC

Base Class Code. It means STE10/100 is a network controller.

02h

RO

23~16

SC

Subclass Code. It means STE10/100 is a Fast Ethernet

Controller.

00h

RO

15~ 8

---

Reserved.

7 ~ 4

RN

Revision Number, identifies the revision number of STE10/

100.

Ah

RO

3 ~ 0

SN

Step Number, identifies the STE10/100 steps within the

current revision.

1h

RO

RO: Read Only.

CR3(offset = 0ch), LT - Latency Timer

31~16

---

Reserved.

15~ 8

LT

Latency Timer. This value specifies the latency timer of the

STE10/100 in units of PCI bus clock cycles. Once the STE10/100

asserts FRAME#, the latency timer starts to count. If the

latency timer expires and the STE10/100 is still asserting

FRAME#, the STE10/100 will terminate the data transaction

as soon as its GNT# is removed.

0

R/W

7 ~ 0

CLS

Cache Line Size. This value specifies the system cache line

size in units of 32-bit double words(DW). The STE10/100

supports cache line sizes of 8, 16, or 32 DW. CLS is used by

the STE10/100 driver to program the cache alignment bits (bit

14 and 15 of CSR0) which are used for cache oriented PCI

commands, e.g., memory-read-line, memory-read-multiple,

and memory-write-and-invalidate.

0

R/W

CR4(offset = 10h), IOBA - I/O Base Address

31~ 7

IOBA

I/O Base Address. This value indicate the base address of PCI

control and status register (CSR0~28), and Transceiver

registers (XR0~10)

0

R/W

6 ~ 1

---

reserved.

0

IOSI

I/O Space Indicator.

1: means that the configuration registers map into I/O space.

1RO

CR5(offset = 14h), MBA - Memory Base Address

31~ 7

MBA

Memory Base Address. This value indicate the base address

of PCI control and status register(CSR0~28), and Transceiver

registers(XR0~10)

0

R/W

6 ~ 1

---

reserved.

Table 4. Configuration Registers Descriptions

Bit #

Name

Descriptions

Default Val

RW Type

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