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CD74HC237E 数据表(PDF) 1 Page - Texas Instruments

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部件名 CD74HC237E
功能描述  High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CD74HC237E 数据表(HTML) 1 Page - Texas Instruments

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Data sheet acquired from Harris Semiconductor
SCHS146C
Features
• Select One of Eight Data Outputs
- Active Low for CD74HC137 and CD74HCT137
- Active High for ’HC237 and CD74HCT237
• l/O Port or Memory Selector
• Two Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13ns at VCC = 5V,
15pF, TA = 25
oC (CD74HC237)
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%, of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
CD54HC237
(CERDIP)
CD74HC137, CD74HCT137, CD74HCT237
(PDIP, SOIC)
CD74HC237
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
Description
The
CD74HC137,
CD74HCT137,
’HC237,
and
CD74HCT237 are high speed silicon gate CMOS decoders
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic.
Both circuits have three binary select inputs (A0, A1 and A2)
that can be latched by an active High Latch Enable (LE) sig-
nal to isolate the outputs from select-input changes. A “Low”
LE makes the output transparent to the input and the circuit
functions as a one-of-eight decoder. Two Output Enable
inputs (OE1 and OE0) are provided to simplify cascading
and to facilitate demultiplexing. The demultiplexing function
is accomplished by using the A0,A1,A2 inputs to select the
desired output and using one of the other Output Enable
inputs as the data input while holding the other Output
Enable input in its active state. In the CD74HC137 and
CD74HCT137 the selected output is a “Low”; in the ’HC237
and CD74HCT237 the selected output is a “High”.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A3
LE
OE1
OE0
GND
Y7
VCC
Y1
Y2
Y3
Y4
Y5
Y6
Y0
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD74HC137E
-55 to 125
16 Ld PDIP
CD74HCT137E
-55 to 125
16 Ld PDIP
CD74HCT137M96
-55 to 125
16 Ld SOIC
CD54HC237F
-55 to 125
16 Ld CERDIP
CD54HC237F3A
-55 to 125
16 Ld CERDIP
CD74HC237E
-55 to 125
16 Ld PDIP
CD74HC237M
-55 to 125
16 Ld SOIC
CD74HC237M96
-55 to 125
16 Ld SOIC
CD74HC237NSR
-55 to 125
16 Ld SOP
CD74HC237PWR
-55 to 125
16 Ld TSSOP
CD74HCT237E
-55 to 125
16 Ld PDIP
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office
or customer service for ordering information.
March 1998 - Revised July 2002
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2002, Texas Instruments Incorporated
CD74HC137, CD74HCT137,
CD54/74HC237, CD74HCT237
High Speed CMOS Logic, 3-to-8 Line Decoder
Demultiplexer with Address Latches
[ /Title
(CD74
HC137
,
CD74
HCT13
7,
CD74
HC237
,
CD74
HCT23
7)
/Sub-
ject
(High
Speed


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