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ST755 数据表(PDF) 4 Page - STMicroelectronics |
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ST755 数据表(HTML) 4 Page - STMicroelectronics |
4 / 9 page APPLICATION CIRCUIT To achieve the best performances from switching power supply topology, particular care to layout drawing is needed, in order to minimize EMI and obtain low noise, jitter free operation moreover, it ensures the full device functionality. Layout design proposed on demoboard (see picture 2) helps to lower the developing time. Wire lengths must be minimized, filter and by-pass capacitors C1,C2 and C3 must be low ESR type, placed as close possible to the integrated circuit. The 10 µH inductor must be chosen built on a core, taking care that saturation current should be higher than the peak LX switch current. See the PEAK INDUCTOR CURRENT vs. LOAD CURRENT graph ( figure 6) Figure 1: TYPICAL APPLICATION CIRCUIT Figure 2: Printed Demoboard Symbol Pin VCC 1 Vout 2 SHDN 3 GND 4 Component Values Capacitor Value Unit Resistor Value Unit C1 47 µFR1 130 K Ω C2 100 µFR2 300 K Ω C3 82 pF R3 10 K Ω C4 1 µFR4 40.7 K Ω C5 10 µFR5 10 K Ω C6 47 pF (*) R1 and R2 can be omitted for Iout<200mA. (**) C6: Very low noise but poor transient and load response speed. (***) C3 (alternative to C6): faster transient and load response. ST755 4/9 |
类似零件编号 - ST755 |
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类似说明 - ST755 |
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