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ST70137TQFP 数据表(PDF) 9 Page - STMicroelectronics |
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ST70137TQFP 数据表(HTML) 9 Page - STMicroelectronics |
9 / 22 page ST70137 9/22 PIN DESCRIPTION Signal Name Direction Init Status Polarity Signal Description PCI INTERFACE PCI_CLK I - - PCI Clock. (33 MHz) The rising edge of this signal is the reference upon which all the other PCI signals are based except for PCI_RSTN and PCI_INTAN. The maximum PCI_CLK frequency for ST70137 is 33MHz and the minimum is DC. PCI_RSTN I I L PCI Reset Reset bring ST70137 in a known state: - All PCI bus output signal tri-stated - All open drain signals floated - All registers set to their factory defaults - All FIFOs emptied - GPIO signals tri-stated - Sachem Macrocell initialized - Clock of Adsl_Up stopped - AFE set in Power down mode PCI_REQN O H L PCI Request This signal is sourced by an agent wishing to become a bus master. It is a point to point signal and each master has its own PCI_REQN. PCI_GNTN I I L PCI Grant The PCI_GNTN signal is a dedicated, point-to-point signal provided to each potential bus master and signifies that access to the bus has been granted. PCI_AD[31:0] I/O I - PCI Multiplexed Address/Data Bus Address and data are multiplexed on the same PCI bus pins. A PCI bus transaction consists of an address phase followed by the one or more data phase. An address phase occurs on the PCLK cycle in which PCI_FRAMEN is asserted. A data phase occurs on PCLK cycles in which PCI_IRDYN and PCI_TRDYN are both asserted. |
类似零件编号 - ST70137TQFP |
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类似说明 - ST70137TQFP |
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