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ST24W16M1TR 数据表(PDF) 8 Page - STMicroelectronics |
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ST24W16M1TR 数据表(HTML) 8 Page - STMicroelectronics |
8 / 17 page Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition termi- nates communication between the ST24/25x16 and the bus master. A STOP condition at the end of a Read command forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. SCL SDA SCL SDA SDA START CONDITION SDA INPUT SDA CHANGE AI00792 STOP CONDITION 1 23 7 89 MSB ACK START CONDITION SCL 1 23 7 89 MSB ACK STOP CONDITION Figure 6. I2C Bus Protocol Data Input. During data input the ST24/25x16 samples the SDA bus signal on the rising edge of the clock SCL. Note that for correct device opera- tion the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Memory Addressing. To start communication be- tween the bus master and the slave ST24/25x16, the master must initiate a START condition. The 8 bits sent after a START condition are made up of a device select of 4 bits that identifie the device type (1010), 3 Block select bits and one bit for a READ (RW = 1) or WRITE (RW = 0) operation. There are three modes both for read and write. They are summarised in Table 4 and described hereafter. A communication between the master and the slave is ended with a STOP condition. 8/17 ST24/25C16, ST24/25W16 |
类似零件编号 - ST24W16M1TR |
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类似说明 - ST24W16M1TR |
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