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SN74ALVCH16821DLR 数据表(PDF) 1 Page - Texas Instruments

部件名 SN74ALVCH16821DLR
功能描述  3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Download  12 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SN74ALVCH16821DLR 数据表(HTML) 1 Page - Texas Instruments

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FEATURES
DESCRIPTION/ORDERING INFORMATION
DGG OR DL PACKAGE
(TOP VIEW)
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1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2CLK
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
SN74ALVCH16821
3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES037F – JULY 1995 – REVISED SEPTEMBER 2004
Member of the Texas Instruments Widebus™
Family
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
This 20-bit bus-interface flip-flop is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH16821 can be used as two 10-bit
flip-flops or one 20-bit flip-flop. The 20 flip-flops are
edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the device
provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to
place the ten outputs in either a normal logic state
(high or low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither load
nor
drive
the
bus
lines
significantly.
The
high-impedance state and increased drive provide the
capability to drive bus lines without need for interface
or pullup components.
OE does not affect the internal operation of the
flip-flops. Old data can be retained or new data can
be
entered
while
the
outputs
are
in
the
high-impedance state.
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Tube
SN74ALVCH16821DL
SSOP - DL
ALVCH16821
-40
°C to 85°C
Tape and reel
SN74ALVCH16821DLR
TSSOP - DGG
Tape and reel
SN74ALVCH16821DGGR
ALVCH16821
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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