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ST10R272LT6 数据表(PDF) 8 Page - STMicroelectronics |
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ST10R272LT6 数据表(HTML) 8 Page - STMicroelectronics |
8 / 77 page 8/77 ST10R272L - PIN DESCRIPTION ALE 36 O 5T Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multi- plexed bus modes. EA 37 I 5T External Access Enable pin. Low level at this pin during and after reset forces the ST10R272L to begin instruction execu- tion out of external memory. A high level forces execution out of the internal ROM. The ST10R272L must have this pin tied to ‘0’. PORT0: P0L.0– P0L.7, P0H.0 - P0H.7 41 - 48 51 - 58 I/O 5T PORT0 has two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. For external bus configuration, PORT0 acts as address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. PORT1: P1L.0– P1L.7, P1H.0 - P1H.7 59- 66 67, 68 71-76 I/O 5T PORT1 has two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. PORT1 acts as a 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. Table 1 Pin definitions Demultiplexed bus modes Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15 Multiplexed bus modes Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15 1 |
类似零件编号 - ST10R272LT6 |
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类似说明 - ST10R272LT6 |
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