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M74HCT651B1R 数据表(PDF) 1 Page - STMicroelectronics |
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M74HCT651B1R 数据表(HTML) 1 Page - STMicroelectronics |
1 / 12 page M74HCT651 M74HCT652 October 1993 HCT652 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE) HCT651 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.) INPUT AND OUTPUT EQUIVALENT CIRCUIT . HIGH SPEED fMAX = 60 MHz (TYP.) AT VCC =5V . COMPATIBLE WITH TTL OUTPUTS VIH = 2 V (MIN.) AT VIL = 0.8V (MAX) . LOW POWER DISSIPATION ICC =4 µA (MAX) AT TA =25 oC . OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE IOH =IOL = 6 mA (mIN.) . BALANCED PROPAGATION DELAYS tPLH =tPHL . PIN AND FUNCTION COMPATIBLE WITH 54/74LS651/652 DESCRIPTION M74HCT651/652 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS (3-STATE), fabricated in silicon gate C 2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. Enable GAB and GBA are provided to control the transceiver functions. Select AB and Select BA control pins are provided to select whether real-time or stored data is transfered. A low input level selects real-time data, and a high selects stored data. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (CLOCK AB or CLOCK BA) regardless of the select or enable control pins. When select AB and select BA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. All inputs are equipped with protection circuits against static discharge and transient excess voltage.This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSCMOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. GAB, GAB, CAB, A, B SAB, SBA, CBA B1R (Plastic Package) ORDER CODES : M74HCXXXM1R M74HCXXXB1R M1R (Micro Package) PIN CONNECTIONS (top view) 1/12 |
类似零件编号 - M74HCT651B1R |
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类似说明 - M74HCT651B1R |
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