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M27W201-80F6 数据表(PDF) 8 Page - STMicroelectronics |
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M27W201-80F6 数据表(HTML) 8 Page - STMicroelectronics |
8 / 16 page M27W201 8/16 Figure 7. Programming Flowchart AI00715D n = 0 Last Addr VERIFY P = 100 µs Pulse ++n = 25 ++ Addr VCC = 6.25V, VPP = 12.75V FAIL CHECK ALL BYTES 1st: VCC = 5V 2nd: VCC = 2.7V YES NO YES NO YES NO PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 26.5 seconds. Pro- gramming with PRESTO II consists of applying a sequence of 100µs program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE at VCC much higher than 3.6V, provides the necessary margin to each programmed cell. Program Inhibit Programming of multiple M27W201s in parallel with different data is also easily accomplished. Ex- cept for E, all like inputs including G of the parallel M27W201 may be common. A TTL low level pulse applied to a M27W201's P input, with E low and VPP at 12.75V, will program that M27W201. A high level E input inhibits the other M27W201s from be- ing programmed. Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. The verify is accomplished with E and G at VIL,P at VIH,VPP at 12.75V and VCC at 6.25V. Figure 6. Programming and Verify Modes AC Waveforms tAVPL VALID AI00720 A0-A17 Q0-Q7 VPP VCC P G DATA IN DATA OUT E tQVPL tVPHPL tVCHPL tPHQX tPLPH tGLQV tQXGL tELPL tGHQZ tGHAX PROGRAM VERIFY |
类似零件编号 - M27W201-80F6 |
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类似说明 - M27W201-80F6 |
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