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M27V512-120N1TR 数据表(PDF) 9 Page - STMicroelectronics |
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M27V512-120N1TR 数据表(HTML) 9 Page - STMicroelectronics |
9 / 16 page 9/16 M27V512 PRESTO IIB Programming Algorithm PRESTO IIB Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 6.5 seconds. This can be achieved with STMicroelectronics M27V512 due to several design innovations described in the M27V512 datasheet to improve programming effi- ciency and to provide adequate margin for reliabil- ity. Before starting the programming the internal MARGIN MODE circuit is set in order to guarantee that each cell is programmed with enough margin. Then a sequence of 100 µs program pulses are ap- plied to each byte until a correct verify occurs. No overprogram pulses are applied since the verify in MARGIN MODE provides the necessary margin. Program Inhibit Programming of multiple M27V512s in parallel with different data is also easily accomplished. Ex- cept for E, all like inputs including GVPP of the par- allel M27V512 may be common. A TTL low level pulse applied to a M27V512’s E input, with VPP at 12.75V, will program that M27V512. A high level E input inhibits the other M27V512s from being pro- grammed. Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. The verify is accomplished with G at VIL. Data should be verified with tELQV after the falling edge of E. Figure 7. Programming and Verify Modes AC Waveforms AI00737 tVPLEL PROGRAM DATA IN A0-A15 E GVPP Q0-Q7 DATA OUT tAVEL tQVEL tVCHEL tVPHEL tEHQX tEHVPX tELEH tELQV tEHAX tEHQZ VERIFY VALID VCC Figure 8. Programming Flowchart AI00738B n= 0 Last Addr VERIFY E = 100 µs Pulse ++n =25 ++ Addr VCC = 6.25V, VPP = 12.75V FAIL CHECK ALL BYTES 1st: VCC =6V 2nd: VCC = 4.2V YES NO YES NO YES NO SET MARGIN MODE RESET MARGIN MODE |
类似零件编号 - M27V512-120N1TR |
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类似说明 - M27V512-120N1TR |
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