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ISL54053_0709 数据表(PDF) 11 Page - Intersil Corporation |
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ISL54053_0709 数据表(HTML) 11 Page - Intersil Corporation |
11 / 11 page 11 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6460.2 September 25, 2007 ISL54053 Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN) B D A E 0.10 C 2X PIN 1 TOP VIEW 0.10 C 2X REFERENCE DETAIL A 0.10 C 0.08 C 7X A3 A1 A C SEATING PLANE 5X L e 1 3 64 4X BOTTOM VIEW SIDE VIEW 0.10 CAB 0.05 C b6X NOTE 3 L1 DETAIL A DETAIL B PIN 1 LEAD 0.1x45° CHAMFER DETAIL B A3 A1 1.40 LAND PATTERN 1.00 0.30 0.35 0.20 0.45 0.40 0.20 10 L6.1.2x1.0A 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE SYMBOL MILLIMETERS NOTES MIN NOMINAL MAX A 0.45 0.50 0.55 - A1 - - 0.05 - A3 0.127 REF - b 0.15 0.20 0.25 5 D 0.95 1.00 1.05 - E 1.15 1.20 1.25 - e 0.40 BSC - L 0.30 0.35 0.40 - L1 0.40 0.45 0.50 - N 6 2 Ne 3 3 θ 0- 12 4 Rev. 2 8/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Ne refers to the number of terminals on E side. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. |
类似零件编号 - ISL54053_0709 |
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类似说明 - ISL54053_0709 |
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