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ISL54047IRUZ-T 数据表(PDF) 7 Page - Intersil Corporation |
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ISL54047IRUZ-T 数据表(HTML) 7 Page - Intersil Corporation |
7 / 12 page 7 FN6503.0 May 31, 2007 Detailed Description The ISL54047 is a bidirectional, differential single pole/single throw (SPST) analog switch that offer precise switching capability from a single 1.65V to 4.5V supply with low on-resistance (0.44 Ω) and high speed operation (t ON = 40ns, tOFF = 35ns). The devices are especially well suited for portable battery powered equipment due to their low operating supply voltage (1.65V), low power consumption (4.5 μW max) and the tiny μTQFN package. The ultra low on- resistance and Ron flatness provide very low insertion loss and distortion to applications that require signal reproduction. External V+ Series Resistor For improved ESD and latch-up immunity Intersil recommends adding a 100 Ω resistor in series with the V+ power supply pin of the ISL54047 IC (see Figure 7). During an over-voltage transient event, such as occurs during system level IEC 61000 ESD testing, substrate currents can be generated in the IC that can trigger parasitic SCR structures to turn ON, creating a low impedance path from the V+ power supply to ground. This will result in a significant amount of current flow in the IC which can potentially create a latch-up state or permanently damage the IC. The external V+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many over voltage transient events. Under normal operation the sub-microamp IDD current of the IC produces an insignificant voltage drop across the 100 Ω series resistor resulting in no impact to switch operation or performance. Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can be protected by adding a 1k Ω resistor in series with the logic input (see Figure 8). The resistor limits FIGURE 5. CROSSTALK TEST CIRCUIT FIGURE 6. CAPACITANCE TEST CIRCUIT Test Circuits and Waveforms (Continued) 0V or V+ ANALYZER V+ C NO SIGNAL GENERATOR RL GND IN1 COM 50 Ω N.C. COM NO Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. V+ C GND NO COM IN IMPEDANCE ANALYZER 0V or V+ Repeat test for all switches. FIGURE 7. V+ SERIES RESISTOR FOR ENHANCED ESD AND LATCH-UP IMMUNITY IN COM1 100 Ω NO1 N02 V+ GND C OPTIONAL PROTECTION RESISTOR COM2 ISL54047 |
类似零件编号 - ISL54047IRUZ-T |
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类似说明 - ISL54047IRUZ-T |
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