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AD8318 数据表(PDF) 11 Page - Analog Devices |
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AD8318 数据表(HTML) 11 Page - Analog Devices |
11 / 24 page AD8318 Rev. B | Page 11 of 24 THEORY OF OPERATION The AD8318 is a 9-stage demodulating logarithmic amplifier that provides RF measurement and power amplifier control functions. The design of the AD8318 is similar to the AD8313 logarithmic detector/controller. However, the AD8318 input frequency range extends to 8 GHz with a 60 dB dynamic range. Other improvements include: reduced intercept variability vs. temperature, increased dynamic range at higher frequencies, low noise measurement and controller output (VOUT), adjustable low-pass corner frequency (CLPF), temperature sensor output (TEMP), negative transfer function slope for higher accuracy, and 10 ns response time for RF burst detection capability. A block diagram is shown in Figure 22. TEMP SENSOR GAIN BIAS SLOPE DET DET DET DET INHI INLO IV VOUT IV VSET CLPF TEMP VPSI ENBL TADJ VPSO CMOP CMIP Figure 22. Block Diagram A fully differential design, using a proprietary high speed SiGe process, extends high frequency performance. Input INHI receives the signal with a low frequency impedance of nominally 1200 Ω in parallel with 0.7 pF. The maximum input with ±1 dB log conformance error is typically 0 dBm (re: 50 Ω). The noise spectral density referred to the input is 1.15 nV/√Hz, which is equivalent to a voltage of 118 μV rms in a 10.5 GHz bandwidth, or a noise power of −66 dBm (re: 50 Ω). This noise spectral density sets the lower limit of the dynamic range. However, the low end accuracy of the AD8318 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. CMIP, the input system common pin, provides a quality low impedance connection to the printed circuit board (PCB) ground via four package pins. Ground the package paddle, which is internally connected to the CMIP pin, to the PCB to reduce thermal impedance from the die to the PCB. The logarithmic function is approximated in a piecewise fashion by nine cascaded gain stages. For a more complete explanation of the logarithm approximation, refer to the AD8307 data sheet. The cells have a nominal voltage gain of 8.7 dB each and a 3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain is stabilized over temperature and supply variations. Because the cascaded gain stages are dc-coupled, the overall dc gain is high. An offset compensation loop is included to correct for offsets within the cascaded cells. At the output of each of the gain stages, a square-law detector cell rectifies the signal. The RF signal voltages are converted to a fluctuating differential current with an average value that increases with signal level. Along with the nine gain stages and detector cells, an additional detector is included at the input of the AD8318, altogether providing a 60 dB dynamic range. After the detector currents are summed and filtered, the function ID × log10(VIN/VINTERCEPT) (1) is formed at the summing node, where: ID is the internally set detector current. VIN is the input signal voltage. VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT, the output voltage would be 0 V if capable of going to 0 V). |
类似零件编号 - AD8318 |
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类似说明 - AD8318 |
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