Rev 1.4, May 25, 2007

Page 3 of 11

SL2305

General Description

The SL2305 is a low skew, low jitter Zero Delay Buffer with

very low operating current.

The product includes an on-chip high performance PLL that

locks into the input reference clock and produces nine (9)

output clock drivers tracking the input reference clock for

systems requiring clock distribution.

In addition to CLKOUT that is used for internal PLL

feedback, there is a single bank with four (4) outputs,

bringing the number of total available output clocks to five

(5).

Input and output Frequency Range

The input and output frequency range is the same. But, the

frequency range depends on the drive levels and load

capacitance (CL) as given in the below Table 1.

Drive

CL(pF)

Min(MHz)

Max(MHz)

HIGH

15

10

140

HIGH

30

10

100

STD

15

10

100

STD

30

10

66

Table 1. Input/Output Frequency Range

If the input clock frequency is DC (0 to VDD), this is

detected by an input detection circuitry and all nine (5) clock

outputs are forced to Hi-Z. The PLL is shutdown to save

power. In this shutdown state, the product draws less than

12 A-max supply current.

SpreadThru

If a Spread Spectrum Clock (SSC) were to be used as an

input clock, the SL2305 is designed to pass the modulated

Spread Spectrum Clock (SSC) signal from its CLKIN

(reference) input to the output clocks. The same spread

characteristics at the input are passed through the PLL and

drivers without any degradation in spread percent (%),

spread profile and modulation frequency.

High and Low-Drive Product Options

The SL2305 is offered with High-Drive “-1H” and Standard-

Drive “-1” options. These drive options enable the users to

control load levels, frequency range and EMI control. Refer

to the AC electrical tables for the details.

Skew and Zero Delay

All outputs should drive the similar load to achieve output-

to-output and input-to-output skew specifications given in

the AC electrical tables.

However, Zero delay between input and outputs can be

adjusted by changing the loading of CLKOUT relative to the

clock outputs since CLKOUT is the feedback to the PLL.

Power Supply Range (VDD)

The SL2305 is designed to operate from 3.0V (Min) to 3.6V

(Max), complying with VDD=3.3V+/-10% requirement.

An internal on-chip voltage regulator is used to supply PLL

constant power supply of 1.8V, leading to a consistent and

stable PLL electrical performance in terms of skew, jitter

and power dissipation.

Refer to SL23EP05 for 2.5V and SL23EPL05 for 1.8V

power supply operation requirements.

Temperature Range and Packages

The

SL2305

is

offered

with

extended

commercial

temperature range of 0 to +70°C (C-Grade) and industrial

temperature range of -40 to +85°C (I-Grade).

The SL2305 is available in 8-pin SOIC (150-mil) and

TSSOP (173-mil) packages.