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ADV3003-EVALZ 数据表(PDF) 10 Page - Analog Devices |
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ADV3003-EVALZ 数据表(HTML) 10 Page - Analog Devices |
10 / 16 page ADV3003 Rev. 0 | Page 10 of 16 THEORY OF OPERATION INTRODUCTION The primary function of the ADV3003 is to buffer the four high speed channels of a single HDMI or DVI link. The HDMI/DVI link consists of four differential, high speed channels and four auxiliary single-ended, low speed control signals. The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10× the data-word clock frequency for data rates up to 2.25 Gbps. All four high speed TMDS channels on the ADV3003 are identical; that is, the pixel clock can be run on any of the four TMDS channels. Receive channel compensation (12 dB of fixed equalization) is provided for the high speed channels to support long input cables. The ADV3003 also includes selectable pre-emphasis for driving high loss output cables or long PCB traces. In the intended application, the ADV3003 is placed between a source and a sink, with long cable runs at both the input and the output. INPUT CHANNELS Each high speed input differential pair terminates to the 3.3 V VTTI power supply through a pair of single-ended 50 Ω on-chip resistors, as shown in Figure 25. When the transmitter of the ADV3003 is disabled by setting the TX_EN control pin as shown in Table 5, the input termination resistors are also disabled to provide a high impedance node at the inputs. Disabl- ing the input terminations when the transmitter is disabled indicates to any connected HDMI sources that the link through the ADV3003 is inactive. CABLE EQ 50Ω TX_EN 50Ω IP[3:0] IN[3:0] AVEE VTTI Figure 25. High Speed Input Simplified Schematic The input equalizer provides 12 dB of high frequency boost. No specific cable length is suggested for this equalization level because cable performance varies widely among manufacturers; however, in general, the ADV3003 does not degrade input signals, even for short input cables. The ADV3003 can equalize more than 20 meters of a 24 AWG cable at 2.25 Gbps, for reference cables that exhibit an insertion loss of −15 dB at the fundamental frequency of this data rate. OUTPUT CHANNELS Each high speed output differential pair of the ADV3003 terminates to the 3.3 V VTTO power supply through two single-ended 50 Ω on-chip resistors, as shown in Figure 26. TX_EN VTTO 50Ω 50Ω OP[3:0] ON[3:0] AVEE IOUT Figure 26. High Speed Output Simplified Schematic The output termination resistors of the ADV3003 back-terminate the output TMDS transmission lines. These back-terminations, as recommended in the HDMI 1.3 specification, act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. For example, interlayer vias can be used to route the ADV3003 TMDS outputs on multiple layers of the PCB without severely degrading the quality of the output signal. |
类似零件编号 - ADV3003-EVALZ |
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类似说明 - ADV3003-EVALZ |
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