XX1001-QK, MTTF (yrs) vs. Backplate Temperature (°C)

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

55

65

75

85

95

Temperature (°C)

18.0-21.0/36.0-42.0 GHz Doubler and

Power Amplifier, QFN, 7x7mm

Page 4 of 5

App Note [1] Biasing

recommended drain currents for each stage.

It is possible to bias each stage separately for greater bias control with the following conditions: Id1<1mA, Id2=20mA, Id3=40mA, Id4=70mA,

Id5=150mA, Id6=270mA. It is recommended to use active biasing to keep the currents constant as the RF power and temperature vary; this gives

the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias circuit may be a single

transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to sense the current. The gate of the

pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltage needed to do this is -0.7V. Typically the gate is

protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative gate bias is available

before applying the positive drain supply.

Recommended Layout

Bias Application Schematic

X1001-QK

Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099

Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com

Characteristic Data and Specifications are subject to change without notice.

©2007 Mimix Broadband, Inc.

Export of this item may require appropriate export licensing from the U.S. Government. In purchasing these parts, U.S. Domestic customers accept

their obligation to be compliant with U.S. Export Laws.

March 2007 - Rev 07-Mar-07

MTTF Tables

MTTF is calculated from accelerated life-time data of single devices and assumes an isothermal back-plate.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

15

17

18

19

20

21

22

23

24

25

26

27

28

RF IN

RF OUT

XX1001-QK

Vg1 (-0.7V)

10 nF

1µF

+

10 nF

1µF

+

10 nF

1µF

+

10 nF

1µF

+

Vd1 (+2.5V)

Vg3,4,5 (-1.2V)

Vg6 (-1.2V)

10 nF

1µF

+

10 nF

1µF

+

10 nF

1µF

+

10 nF

1µF

+

Vg2 (-0.5V)

Vd2 (+3V)

Vd3,4,5 (+ 4.5V)

Vd6 (+ 4.5V)

Pin

VD1

VD2

VD3,4,5

VD6

Voltage (V)

2.5

3.0

4.5

4.5

Current (ma)

<1

20

260

270

Comment

Drain Bias (Doubler)

Drain Bias (Buffer Amp)

Drain Bias (PA)

Drain Bias (PA - final stage)