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74LV259DB 数据表(PDF) 4 Page - NXP Semiconductors |
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74LV259DB 数据表(HTML) 4 Page - NXP Semiconductors |
4 / 19 page 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 4 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 6. Functional description D 13 data input LE 14 latch enable input (active LOW) MR 15 conditional reset input (active LOW) VCC 16 supply voltage Table 2. Pin description …continued Symbol Pin Description Table 3. Mode select table H = HIGH voltage level; L = LOW voltage level LE MR Mode L H addressable latch H H memory L L active HIGH 8-channel demultiplexer H L reset Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = High or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q<n> = state of the output established during the last cycle in which it was addressed or cleared Operating modes Input Output MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 master reset L H X X X X L L L L L L L L demultiplex (active HIGH) decoder (when D = H) L L d L L L Q = d L L L L L L L L L d H L L L Q = d L L L L L L L L d L H L L L Q = d L L L L L L L d H H L L L L Q = d L L L L L L d L L H L L L L Q = d L L L L L d H L H L L L L L Q = d L L L d L H H L L L L L L Q = d L L L d H H H L L L L L L L Q = d store (do nothing) H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 addressable latch H L d L L L Q = d q1 q2 q3 q4 q5 q6 q7 H L d H L L q0 Q = d q2 q3 q4 q5 q6 q7 H L d L H L q0 q1 Q = d q3 q4 q5 q6 q7 H L d H H L q0 q1 q2 Q = d q4 q5 q6 q7 H L d L L H q0 q1 q2 q3 Q = d q5 q6 q7 H L d H L H q0 q1 q2 q3 q4 Q = d q6 q7 H L d L H H q0 q1 q2 q3 q4 q5 Q = d q7 H L H H H H q0 q1 q2 q3 q4 q5 q6 Q = d |
类似零件编号 - 74LV259DB |
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类似说明 - 74LV259DB |
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